Analysis And Modeling Of Digital Systems Zainalabedin Navabi Pdf Upd | Vhdl

The book treats VHDL not as a programming language, but as a rooted in discrete event simulation.

| Aspect | Simulation Model | Synthesizable Model | |--------|----------------|---------------------| | Timing | AFTER , TRANSPORT , REJECT | Ignored | | Data types | FILE , ACCESS , STRING | BIT , STD_LOGIC , INTEGER | | Loops | Unlimited WHILE | Fixed bounds ( FOR with static range) | | Initialization | Variables at declaration | Use reset signal |

entity and2 is port (a, b : in bit; y : out bit); end and2;

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