Replaces the traditional NRZ (Non-Return-to-Zero) signaling. Instead of two voltage levels (0 or 1), PAM4 uses four levels, allowing it to carry 2 bits of data in the same time interval. FLIT Mode (Flow Control Unit):
, this standard ensures backward compatibility while introducing Forward Error Correction (FEC) and the L0p power state for improved efficiency . Review the official release announcement at PCI Express 6.0 Specification pci express base specification revision 60 pdf
Integrated to minimize burst errors.
Historically, PCIe used 128b/130b encoding (PCIe 3.0–5.0), which means for every 130 bits sent, 128 were data and 2 were overhead for frame synchronization. Replaces the traditional NRZ (Non-Return-to-Zero) signaling
Because PAM4 is inherently noisier, PCIe 6.0 introduces as a mandatory feature. Review the official release announcement at PCI Express 6
, marks a transformative shift in high-speed interconnect technology. It doubles the data rate of its predecessor to 64 GT/s, achieving up to 256 GB/s of bidirectional bandwidth in a x16 configuration.
The is not merely an incremental update; it is a fundamental re-architecture of how the most popular interconnect on earth operates. By shifting to PAM4 signaling and FLIT mode with FEC , PCIe 6.0 abandons a 20-year signaling paradigm to achieve 64 GT/s.